- MOSIS SCMOS Cell Documentation
- SRC FreePDK Documentation
FreePDK: Unleashing VLSI to the Masses
OSU Design Flows for MOSIS SCMOS_SUBM Design Flow
FreePDK 45nm Variation-Aware Design Flow
for use with Magic, Cadence, Synopsys, and MOSIS
Welcome! The following pages give information regarding design flows for System on Chip designs that were developed for use at Oklahoma State University for use with MOSIS SCMOS_SUBM process.
We have also developed jointly with North Carolina State University FreePDK45nm, a Variation-Aware 45nm Design Flow for the Semiconductor Research Corporation. The SRC version is designed with Synopsys' Cadabra and allows full-chip synthesis and place & route through CDS Encounter. You can download the design flow and standard cell library here and the technology kit from North Carolina State University here: NCSU_FreePDK45nm.
The OSU MOSIS SCMOS distribution (v2.7) includes Mentor Graphics, Synopsys and Cadence Design Systems support. Also, please check out Wiki from link. Tutorials are being converted to Wiki to allow user input modifications.
ChipTalk is now active where researchers, students, and all interested can get help, information, and support for the use of our flows. It is available via the link above or at the following site: http://www.chiptalk.org.
SCMOS Supported Technologies:
- AMI 0.5um (with pad cells)
- AMI 0.35um (with pad cells)
- TSMC 0.25um
- TSMC 0.18um
Provided files:
- Timing Libraries: LIB, DB, TLF
- Simulation Libraries: Verilog, VHDL
- Geometry Libraries: LEF
- Cell layouts: Virtuoso, Magic, GDS2, CIF
We also developed an ASIC design flow for the following tools
- Synopsys Design Compiler
- Cadence PKS
- Synopsys Physical Compiler
- Synopsys Astro
- Cadence Silicon Ensemble
- Cadence SOC Encounter
The design flow requires the NCSU design kit or other design kits available from MOSIS.
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