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More Information about the OSU Design Flow

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A summary of the enhancements that our cell library provides:

• Freely available for all .edu sites
• Mailing list that provides access to all participants and instant news on possible enhancements and release dates for future generations of the library.
• Layouts of the leaf cells
• Characterized for delay and power. Area inserted into Synthesis file for possible area-sensitive synthesis runs.
• Tutorials listed at this site that document step-by-step procedure for users aimed for student use.
• Synopsys synthesis (.db) and Verilog/VHDL simulation libraries
• Cadence TLF timing libraries
• LEF files for the P&R tool
• All abstracts from CDS' Abstract Generator
• Macro-routing through Encounter.
• Various drive strengths.
• Documentation that lists power, area, and speed for each device and technology.
• Scripts that automate the procedure and are easy for students to use.
• Scripts that automate insertion and simulation into public-domain and commerical tools.
• Distribution enables Synopsys DesignWare (module compiler) components to be instantiated.
• Verified through MOSIS multiple times with Pad Frame provided by MOSIS.
• Wiki Support

Directory structure

• All of the cells are organized into one tar-ball that contains each technology as a directory. The tutorials that are available from the link at the bottom of this web page contain a step-by-step description on their use. Each main/ directory includes the principle files. The scripts listed below will also copy the necessary leaf cells where you are working. Scripts and batch files are used to encourage script usage to students although GUI's can still be utilized.
• Also included are a number of reference designs, implemented with the OSU System on Chip design flow. A small RISC core was obtained from Opencores.com and implemented in all technologies, as well as with Pads for 0.5 and 0.35. A Newton-Raphson ALU was implemented as well. DFII libraries for all designs are included, as well as all scripts to re-run the flow.
• The "accu" reference design is a simple accumulator. It demonstrates an ASIC flow using Magic and IRSIM, including post-route switch-level simulation through the pad-frame. Useful for first-time VLSI students.

  ./osu_stdcells/flow/ami05
  ./osu_stdcells/flow/ami035
  ./osu_stdcells/flow/tsmc025
  ./osu_stdcells/flow/tsmc018
  
  ./osu_stdcells/ref_designs/encounter
  ./osu_stdcells/ref_designs/se
  ./osu_stdcells/ref_designs/magic6
  

Included scripts

We created a number of scripts to speed up several tasks an ASIC designer typically encounters. They are included in the standard cell release:

• se_shell - Wrapper to run Silicon Ensemble in batch mode
• osucells_se2magic - Creates a Magic 6.5 layout from Silicon Ensemble output
• osucells_se2magic7 - Creates a Magic 7.3 layout from Silicon Ensemble output
• osucells_se2icfb - Creates a DFII library for Virtuoso from Silicon Ensemble output
• osucells_enc2magic - Creates a Magic 6.5 layout from Cadence Encounter output
• osucells_enc2magic7 - Creates a Magic 7.3 layout from Cadence Encounter output
• osucells_enc2icfb - Creates a DFII library for Virtuoso from Cadence Encounter output
• osucells_polyresfix - Fixes the polysilicon resistor in Magic designs with pads
• osucells_scalesim - Scales a .sim file back to the full lambda grid
• osucells_ext2sim - Combines polyresfix and scalesim into a convenient script
• osucells_spice2sim - Converts a SPICE netlist to a SIM netlist for use with IRSIM.
• osucells_mapperbus - Convert a Cadence mapfile (for a flat netlist) to irsim vector definitions